Thermal cycling of chalcogenide materials (Ge2Sb2Te5 or GeSb for example) causes switching between two electrical resistance levels in the materials. This is the basis of PC memory, and offers the possibility of use for programmable signal switching in electronic systems as well. Here we propose a design for connection topology, using dual tip AFM-type probes. The design subdivides a single phase change via into a parallel array of three-terminal sub-vias which are well-suited to addressing with probes. This sub-division reduces required power and current to acceptable levels. Experimental inputs to the model were extracted from two sources. First, current levels were limited to levels that have previously been shown possible to deliver with AFM tips. Secondly, measurements of PC resistance as a function of cooling time were used to determine required heat sinking of the sub-via structures.

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