Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

1.
Abhijit Kaisare, Dereje Agonafer, A. Haji-shiekh, Greg Chrysler and Ravi Mahajan, “Thermal based optimization of functional block distributions in a non-uniformly powered die,” published in InterPACK conference, 2005.
2.
Abhijit Kaisare, Dereje Agonafer, A. Haji-shiekh, Greg Chrysler and Ravi Mahajan, “Design rule for minimizing thermal resistance in a non-uniformly powered microprocessor,” published in SEMITHERM conference, 2006.
3.
Teck Joo Goh, A.N. Amir, Chia-Pin Chiu and J. Torresola, “Novel thermal validation metrology based on non-uniform power distribution for Pentium(R) III XeonTM cartridge processor design with integrated level two cache,” 51st Electronic Components and Technology Conference, 2001, pp. 1181–1186.
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