Following Moore's law, the number of transistors on a die continues to rise and has recently exceeded a billion on high end processors. In light of the convergence of technology, power requirements is becoming a serious concern even on low density interconnect systems such as cellular phones and personal digital assistants. Also, in order to minimize foot prints, the recent trend in packaging is stacking. The stacking, however, creates challenges in cooling and especially if one is to include logic in the stack. The primary heat flow path for stacking is through the substrate and as the number of stacks increase, the cooling problem is amplified. Thermal vias are emerging as a viable technology for transferring heat and in effect creating a thermal short circuit from individual die to the substrate. Some of the authors of this paper earlier reported on the reliability of stacked memory dies. In a subsequent paper the thermal reliability that included geometrical stacking architecture (rotating, spacer, ..) and the inclusion of both logic and memory dies was addressed. In this present paper, the heat transfer enhancement using silicon vias on various stacking schemes is discussed. The CAD models required for this study were developed in Pro/Engineer® Wildfire™ 2.0 and for the result simulation ANSYS® Workbench™ 10.0 have been used. Packaging architectures that have been taken in to consideration are die, solder ball, substrate, mold cap and thermal vias.

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Cooling Zone: Web reference:
Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor, Bhavani P. Dewan-Sandur
Intel Technology Journal (ITJ)-Vol. 9, Issue 4,
Pro/E® WildFire™ 2.0 Reference Manual
Ansys® WorkBench™ 10.0 Reference Manual
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