Lead-free (Pb-free) solder has seen increasing use in interconnect systems for electronic packages due to legislative and marketing pressures. The NEMI selected eutectic Sn3.9Ag0.6Cu alloy (or a close variation near eutectic Sn3.5Ag1.0Cu used in this study) is a leading Pb-free substitute for the Sn/Pb solder candidate. The reliability of this Pb-free solder alloy under accelerated thermal cycling and thermal shock testing as a function of testing parameters such as dwell time and ramp rate is critical in qualifying the performance of these Pb-free alternatives with the traditionally used Sn37Pb solder This paper presents the reliability of Pb-free solder joints in wafer level chip scale packages (WLCSPs), which are extensions of flip-chip packaging technology to standard surface mount technology, with external dimensions equal to that of the silicon device [1]. The reliability of these packages under both liquid-to-liquid thermal shock (LLTS) testing and accelerated air-to-air thermal cycling (AATC) conditions, as a function of dwell times and ramp rates is evaluated using extensive experimental testing in combination with finite element analysis. Besides, two asymmetric cycles in which the cold and hot dwell times differ at two temperature extremes were studied. Along with the Pb-free solder, some test vehicles were built using eutectic Sn-Pb solder and evaluated for comparison purposes. Experimental results show that an increase in ramp rate does not adversely affect the solder joint reliability in the case of Pb-free solder. The reliability of lead-free WLCSPs was highly dependent upon the dwell time at the temperature extremes, with this dependency being considerably greater for the lead-free allow than for Sn/Pb at 0°C and 100°C. Accelerated test results show that increasing the dwell time from 280 to 900 seconds reduced the N63.2 of the Sn/Pb samples by 12% and the Pb-free samples by 65%. Reliability during asymmetric cycles resulted in a trend that is similar in two cases studied. A predictive equation was developed to evaluate the characteristic life of the package with respect to the dwell time. Non-linear, finite element (FE) modeling was conducted using temperature dependent creep constitutive relations for the Pb-free solder to understand the experimental trends observed. The FE results predicted the same trend of the package reliability as observed experimentally, with respect to the changing dwell and ramp times. The finite element predictions demonstrated reasonable correlation with the experimental observations.

1.
Pitarresi, J., Chaparala, S., Sammakia, B.G., “A Parametric Predictive Solder Joint Reliability Model for Wafer-Level Chip Scale Package”, Proceedings of 52nd Electronic Components Technology Conference (ECTC), San Diego, 2002.
2.
Sastry, V. S., Manock, J C., and Ejim, T I., “Effect of Thermal Cycling Ramp Rates on Solder Joint Fatigue Life”, Journal of SMT, 2001, pp.23–28.
3.
Chaparala
S.
,
Roggeman
B.
,
Pitarresi
J.
,
Sammakia
B.
, “
Effects of Geometry and Temperature Cycle on the Reliability of Wafer level Chip scale Package Solder Joints
”,
IEEE Transactions on Components pckaging and Manufacturing Technology
, Vol.
28
, No.
3
, September
2005
, pp.
441
448
.
4.
Charlie
J.
,
Zhai
Sidharth
, and
Blish
Richard
Board Level Solder Reliability Versus Ramp Rate and Dwell time During Temperature Cycling
”,
IEEE Transactions on Device and Materials Reliability
, Vol.
3
, No.
4
, December
2003
, pp.
207
212
.
5.
Amagai
M.
, “
Chip scale Package Solder Joint Reliability and Modeling
”,
Microelectronics Reliability
, Vol.
39
,
1999
, pp.
463
477
.
6.
Xuejin Fan, George Raiser, Vasu S. Vasudevan, “Effect of Dwell Time and Ramp Rate on Lead-Free Solder Joints in FCBGA Packages”, 55th Electronic Components and Technology Conference, 2005, pp.901–906.
7.
Schubert, A., et al., “Fatigue Life Models of SnAgCu and SnPb Solder Joints Evaluated by Experiments and Simulations,” Proceedings of 53nd Electronic Components Technology Conference (ECTC), New Orleans, 2003, pp.603–610.
8.
Zhang, Q., et al., “Viscopleastic Constitutive Properties and Energy Partitioning Model of Lead-free Sn3.9Ag0.6Cu Solder Alloy,” Proceedings of 53nd Electronic Components Technology Conference (ECTC), New Orleans, 2003, pp.1862–1868.
9.
Armstrong, W., et al “Constitutive Relationship Development, Modeling and Measurement of Heat Stressing of MicroSMD Assembly with Sn3.9Ag0.6Cu Alloy,” ASME INTERPACK, July 2005, San Francisco.
10.
Morris, J W., et al., “Creep Properties of Sn-rich Solder Joints,” Proceedings of 53nd Electronic Components Technology Conference (ECTC), New Orleans, 2003, pp.54–57.
11.
Syed, A., “Accumulated Creep Strain and Energy Density Based Thermal Fatigue Life Prediction Models for SnAgCu Solder Joints”, 54th Electronic Components and Technology Conference, 2004, pp.737–746.
12.
ANSYSTM is a registered trade mark.
13.
Ghaffarian, R., “CSP Assembly Reliability after Accelerated thermal and Mechanical cycling,” Chip Scale Review, November 2000.
This content is only available via PDF.
You do not currently have access to this content.