Warpage has long been known to cause thermomechanical reliability problems in electronic packaging. The coefficient of thermal expansion (CTE) mismatch between different materials in an electronic assembly such as solder, copper, FR-4, encapsulation molding, and silicon is known to be one of the leading causes of manufacturing defects and fatigue failures. The CTE mismatch between packaging materials induces thermomechanical stresses at interfaces between the materials. Warpage is a global effect of interfacial stress and displacement. The warpage problem in electronic packaging can be further aggravated by thermal processes such as reflow and temperature cycling. In a printed wiring board assembly (PWBA), warpage of the PWB or chip packages may result in chip package misregistration, solder joint failure, die cracking and delamination of the solder bumps between chip packages and the PWB. In this paper, the warpage of a printed wiring board assembly (PWBA) is studied using projection moire´ experimental measurements and a finite element model. The effects of plastic ball grid array (PBGA) chip package placement on PWB warpage during convective reflow will be evaluated. The projection moire´ experimental warpage results will show that the number of PBGA chip packages as well as their location has an effect on the warpage of the PWB. In addition to the experimental results, the finite element warpage results will be used to make recommendations on the optimal PBGA package placement locations on the PWB to minimize PWB warpage during reflow processes.

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