With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

1.
D.S. Jiang et al, “Underfill Selection and Validation for Low K Chips”, 6th International Conference on Electronics Materials and Packaging, 2004.
2.
Yong. Du et al, “Thermal Stress and Debonding in Cu/Low k Damascene Line Structure”, Interfacial Adhesion Study for Low-k Interconnects in Flip-chip Packages” Proc. 52th Electronic Components and Technology Conference, 2002, pp. 859–864.
3.
Lei L. Mercado et al, “Analysis of Flip-Chip Packaging Challenges on Copper Low-k Interconnects”, 53th Electronic Components and Technology Conference, 2003, pp. 1784–1790.
4.
Seung Wook Yoon et al, “UBM Integrity Studies on Copper/low-k Dielectrics for Fine Pitch Flip Chip Packaging”, 53th Electronic Components and Technology Conference, 2003, pp. 1222–1229.
5.
Seung Wook Yoon et al, “Flipchip Bump Integrity with Copper/Ultra Low-k Dielectrics for Fine pitch Flipchip Packaging”, 53th Electronic Components and Technology Conference, 2003, pp. 1636–1641.
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