This manuscript investigates the relevance and impact of nanoscale thermal phenomena in the state-of-the-art semiconductor device technologies such as: silicon-on-insulator (SOI), strained silicon, and tri-gate CMOS transistors. The experimental data and predictions for thin silicon layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in strained-Si/Ge bi-layer configuration are used to estimate the thermal resistance of the SOI, tri-gate, and strained-silicon-on-SiGe-on-insulator (SGOI) transistors, respectively. In particular, the impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the silicon layer at room temperature is investigated. In order to avoid the complexity of the BTE for predictions of the temperature distribution, Lumped Analytical (LA) models are introduced that are simple to implement and also adequate enough to capture the sub-continuum effects. It is concluded that the SOI, SGOI and tri-gate transistors are all susceptible to self-heating for very thin silicon device layers.

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