Effect of Microprocessor Features in Control Loops Modeled in Simulink Available to Purchase

The intensive use of simulation tools, such as simulink has made possible the development of embedded controllers using a plant model as a base. The performance in the simulation environment does not account however for the details of the hardware architecture. In this paper, a way to approximate some of the effects of the features of a particular microprocessor is derived for the Simulink environment. Worst-case execution time of the given control algorithm is performed as the first step. The computation error is also estimated for that particular algorithm. A block in the Simulink model could then express the computation latency due to hardware processing and the error due to computation accuracy. An automatic way of estimating these effects is presented here in order to achieve a higher integrability of software tools available for the designer. In particular, controller design involves deciding what hardware platform to choose for a particular application. Analysis and experimental results of a particular microprocessor are discussed.