This paper presents thermal stress simulation results for a monolithic pressure sensing element design. The basic design concept is to fabricate a standard submicron CMOS process with appropriate modifications to integrate on-chip signal conditioning circuits with piezoresistive sensing elements with anisotropic-etched diaphragms. The stress simulation is used to estimate the electromechanical behavior of a new monolithic sensing element design. The major tasks are to predict ripple deformation of the silicon diaphragm due to thermal residual stresses from multiple passivation layers, find an optimal placement location for the piezoresistive transducer with the highest stress sensitivity or largest full scale span (FSS), and estimate the pressure nonlinearity.

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