As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.
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ASME 2002 International Mechanical Engineering Congress and Exposition
November 17–22, 2002
New Orleans, Louisiana, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
0-7918-3648-7
PROCEEDINGS PAPER
A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect Available to Purchase
Qi Zhu,
Qi Zhu
Georgia Institute of Technology, Atlanta, GA
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Lunyu Ma,
Lunyu Ma
Georgia Institute of Technology, Atlanta, GA
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Suresh K. Sitaraman
Suresh K. Sitaraman
Georgia Institute of Technology, Atlanta, GA
Search for other works by this author on:
Qi Zhu
Georgia Institute of Technology, Atlanta, GA
Lunyu Ma
Georgia Institute of Technology, Atlanta, GA
Suresh K. Sitaraman
Georgia Institute of Technology, Atlanta, GA
Paper No:
IMECE2002-39679, pp. 353-359; 7 pages
Published Online:
June 3, 2008
Citation
Zhu, Q, Ma, L, & Sitaraman, SK. "A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect." Proceedings of the ASME 2002 International Mechanical Engineering Congress and Exposition. Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology. New Orleans, Louisiana, USA. November 17–22, 2002. pp. 353-359. ASME. https://doi.org/10.1115/IMECE2002-39679
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