FR4 has been extensively used as a board material due to its cost effectiveness and overall performance. For high-density wiring (HDW) substrates with microvias and with embedded capacitors, inductors, resistors, RF and optoelectronic waveguides in a single board, there is a need for alternative base substrates to meet the stringent warpage requirements during fabrication. Typically, these base substrate materials should have high modulus, good planarity, in addition to having a CTE that is close to that of silicon so that the flip-chips can be directly attached to the substrate, eliminating the need for an underfill. Although low-CTE, high modulus base substrate materials can eliminate the need for underfill as well as can result in less warpage during fabrication, they can potentially cause delamination and cracking in the interlayer dielectric. This is due to the high CTE mismatch between the base substrate and typical polymer dielectric. This paper aims to explore a combination of base substrate materials and interlayer dielectric materials such that warpage is minimal, dielectric will not crack or delaminate, and flip-chip solder joints, assembled without an underfill, will not crack prematurely during qualification regimes and operating conditions. A non-liner finite element model with Design-of-Simulations approach is used in arriving at optimized thermo-mechanical properties for the base-substrate and dielectric materials to enhance the overall reliability of the integrated substrate with flip chip assembly. The results from the models have been compared with experimental data and a discussion is presented on the various failure modes.

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