Stress voiding is a common defect of the semiconductor interconnect. In thermal cycles, other defects such as the hillocks, delamination can also occur. For the Cu/low-k interconnect, simulation with Ansys is made to analysis the interconnect stress-strain distribution and deformation. Results indicate that stress induced void is prone to form in the via than in the metal lines. Flower defect appear at the via top can also be analyzed based on the stress distribution. It is found that Von-Mises stress represent the localization of the stress concentration, which cause delamination and over-stress failure at the interface of the different materials.

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