Wafer Level Packaging (WLP) of microelectronic circuitry, in which critical package elements are formed on the silicon wafer prior to dicing, has several advantages over conventional packaging techniques, such as one-step testability of multiple chips on a silicon wafer prior to dicing, and the possibility of high input-output (I/O) density. One of the critical elements of WLP is the interconnect. Freely movable interconnects, which act like springs when thermally and mechanically loaded, can be used to relieve thermal and bonding-generated stresses, potentially resulting in improved testablility and reliability in WLP. In this work, flexible free-standing and no-underfill inteconnects were fabricated in a CMOS-compatible surface micromachining technology directly on a silicon wafer. The compliance of these interconnects up to 50 microns in the direction normal to the wafer was measured. Deflections and thermal expansions under mechanical-thermal stress were also simulated using finite element methods. Good agreement was achieved between the measured compliance and that predicted by the finite element analysis.

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