Dimensional variation is inherent in manufacturing and it is impossible to attain exact nominal dimensions. Ideally, designer should accommodate this variation likelihood in design stage and define an allowable variation. This allowable variation is represented as tolerances and is either considered a bounded zone or a scaled allowable process standard deviation (e.g. 6 times standard deviation). The allowable tolerances are usually constrained by assemblability, functionality and manufacturing economics. Meeting these constraints simultaneously becomes a paramount task and designers usually never consider production economics when specifying tolerances. As a consequence rarely do the tolerances specified by product designer match that of the process designer. Automated tolerance value allocation can empower the product designer to include all the constraints at the design phase and reduce the overall time line between development to production. Automated tolerance allocation method described in this paper is intended for use by the designer and encompasses only 1st order tolerancing. The Critical stack detection/loop detection tool extracts the assembly level stacks that dictate assemblability. The allocation tool utilizes these stacks to distribute tolerance budget by a rule of thumb. These stacks are subjected to variation analysis to compute acceptance rates and used as feedback for iterative reallocation using a hill climbing optimization algorithm till statistical fit requirements are satisfied or allocation gets exhausted. The algorithm is tested on some case studies and presented in the paper.
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ASME 2016 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference
August 21–24, 2016
Charlotte, North Carolina, USA
Conference Sponsors:
- Design Engineering Division
- Computers and Information in Engineering Division
ISBN:
978-0-7918-5011-4
PROCEEDINGS PAPER
Automated Iterative Tolerance Value Allocation and Analysis
Deepanjan Biswas,
Deepanjan Biswas
Arizona State University, Tempe, AZ
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Adarsh Venkiteswaran,
Adarsh Venkiteswaran
Arizona State University, Tempe, AZ
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Sayed Mohammad Hejazi,
Sayed Mohammad Hejazi
Arizona State University, Tempe, AZ
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Jami J. Shah,
Jami J. Shah
Arizona State University, Tempe, AZ
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Joseph K. Davidson
Joseph K. Davidson
Arizona State University, Tempe, AZ
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Deepanjan Biswas
Arizona State University, Tempe, AZ
Adarsh Venkiteswaran
Arizona State University, Tempe, AZ
Sayed Mohammad Hejazi
Arizona State University, Tempe, AZ
Jami J. Shah
Arizona State University, Tempe, AZ
Joseph K. Davidson
Arizona State University, Tempe, AZ
Paper No:
DETC2016-60145, V02BT03A019; 14 pages
Published Online:
December 5, 2016
Citation
Biswas, D, Venkiteswaran, A, Hejazi, SM, Shah, JJ, & Davidson, JK. "Automated Iterative Tolerance Value Allocation and Analysis." Proceedings of the ASME 2016 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. Volume 2B: 42nd Design Automation Conference. Charlotte, North Carolina, USA. August 21–24, 2016. V02BT03A019. ASME. https://doi.org/10.1115/DETC2016-60145
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