For practical applications, the fractional order integral and differential operators require to be approximated as stable, causal, minimum-phase integer order systems, which usually leads, in both continuous and discrete domains, to high order transfer functions. Assuming that an approximation of good quality is available for the fractional operator, efficient implementations, in both cost and speed, are required. The fast development of the microelectronics gives us the opportunity of using cheap, accurate, programmable and fast devices for implementing reconfigurable analog and digital circuits. Among these devices, Field Programmable Gate Arrays (FPGAs), Switched Capacitors Circuits (SCCs), and Field Programmable Analog Arrays (FPAAs) are used in this paper for the implementation of a fractional order integrator, previously approximated by the recursive Oustaloup’s method. The fundamentals of the devices, as well as the design procedures are given, and the implementations are compared considering their simulated frequency responses, the design efforts, and other important issues.

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