Control of complex structures requires high computational power to achieve real-time performance. Through decentralized techniques, a complex structure can be controlled by multiple lower-order local controllers, leading to reduced computational complexities. Furthermore, a decentralized approach can both simplify the development of parallel controllers and facilitate fault-tolerant designs. In our research, multiple digital signal processors are employed in a NASA-sponsored segmented telescope testbed to increase the throughput of control tasks. Although increased performance is realized when subsystems are statically mapped to specific processors for control, inefficiency arises if the number of subsystems M is not an integer multiple of the number of processors P (M > P) because (M mod P) processors are necessarily controlling more subsystems than others. Optimality is sacrificed because processors with lighter loads wait for processors with heavier loads. Furthermore this mechanism does not lend itself favorably towards fault tolerance because the failure of a single processor will result in the failure of its subsystem. This paper describes the design and implementation of a pipelined task mapping approach for the decentralized control of a segmented reflector telescope testbed. In our pipelined processing implementation only four of the six subsystems are processed in any given control cycle; the two unprocessed subsystems in each cycle propagate about the system in a round-robin fashion, so processors are never idle. Fault tolerance is facilitated because processors are no longer tied to specific subsystems. Instead, control computations are distributed dynamically such that the pipeline flow structure is maintained. The implementation of a watchdog technology is presented for detecting the possible processor failures. Experimental results are shown comparing the performance of the pipelined and straightforward approaches. The throughput of the system has also been estimated on a system with a larger number of processors. Such estimation shows the linearity of speedup achieved by using the pipelined approach.

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