The objective of this study is to empirically investigate the dependence of solder voids and related interconnect defects in QFN packages, on such design variables as stencil aperture pattern and size, as well as quantity and location of thermal vias. A non-traditional fractional-factorial matrix was used for this study. The QFN packages produced by implementing this experiment were analyzed using destructive and nondestructive failure analysis techniques. The effect of design variables on different types of defects such as voids, and taper were evaluated. This study showed that stencil aperture size influences void area percentage the most in comparison with other design variables. An optimal stencil configuration was proposed based on void area fraction calculations. A 2-D steady-state finite element analysis was then conducted to parametrically evaluate the effect of solder voids on the performance of thermal vias under QFN thermal pads. The model confirmed that the performance of thermal vias is not very sensitive to void area fraction.

This paper describes the effect of hole shape on the flow resistance of perforated plates used in electronic equipment in the low Reynolds number region such as natural convection. Measurement of 16 types of perforated plates and analysis of the results were conducted using the Design of Experiments (DoE) method. In the range of levels of DoE analysis assumed for electronic equipment, it was found that hole shape has little effect on flow resistance in the low Reynolds number region.

Compact Thermal Models (CTMs) are multi-nodal thermal resistor networks which predict the internal thermal response of an electronic package, in various environments, to within an accuracy of 2%. The junction temperature of the package is typically obtained by solving a set of linear algebraic equations wherein the heat transfer to the ambience is modeled by a convection coefficient obtained from hand-book data, assuming identical ambient conditions imposed at all nodal surfaces. In reality, this approach may give misleading results as the ambience at each of the nodal surfaces is different and depends on the cooling fluid flow behavior at that surface. In this work, a methodology is presented where the network equations of the CTMs are coupled with the governing fluid equations solved by computational fluid dynamics (CFD). The CTM+CFD approach predicts a significantly (28%) higher junction temperature as compared to the conventional CTM network solver method, even when the convection coefficient used in the latter is obtained more accurately from CFD, rather than from hand-book correlations. It is likely that the new approach offers a more effective prediction of the package thermal performance.

In the present study, the robust thermal design of a power device package was accomplished using thermal conduction calculation, design of experiment, response surface method and Monte Carlo simulation. Initially, the effects of the design parameters on the solder strain were examined in terms of the thermal expansion difference as a result of unsteady thermal conduction simulation. From the factorial effects of design parameters, the design proposals were screened. Then, robustness of the thermal resistance was evaluated for the three design proposals obtained. The thermal resistances were calculated by solving the steady thermal conduction equation under the design of experiment conditions. The solder thickness, the substrate thickness, and the cooling fin performance were considered as the fluctuation factors, assuming the error associated with manufacturing process. Using a response surface method, the values of thermal resistance were expressed as a function of the design variables. The variances of the thermal resistance were examined based on Monte Carlo simulations. Related to the cooling fin design, the Pareto line showing the trade-off relation between the fin dimension and the fan velocity was obtained. By repeating the Monte Carlo simulations, the Pareto solution was calculated so that the thermal resistances satisfy the criteria in the position of 95 percrntile of the thermal resistance variation. Under the same flow velocity conditions, the fin dimensions become about 10% higher compared to the case where the manufacturing error was not taken into account. By carrying out the thermal design following this Pareto line, even if the manufacturing error was taken into consideration, the thermal resistance could satisfy the desired value.

A general method was developed to predict the condenser temperature at each power load. And a simulation program and infrared camera was used to study the flow characteristics. High density polyethylene porous material was added in the evaporator to CPL, the loop was designed on the ground with a horizontal position and scale down the whole device to the miniature size. From the experimental results, the CPL could remove heat 110W in steady state and keep the heat source temperature about 80°C. Finally, a good agreement between the simulation and experimental values has been achieved. Comparing with experiment and simulation results, the deviation values of the distributions of the condenser outlet temperature are less than 5%.

We here present the results of an effort to determine the influence of the parameters affecting cold-plate performance and to minimize the total thermal resistance of a CPU cold-plate. An analysis based on analytical calculations and CFD simulations shows that spreading resistance is affected not only by the heat source area, cold-plate thickness and thermal conductivity of the cold-plate material, but also by the effective heat transfer coefficient of the interface between cold-plate and cooling liquid. Different options for optimizing heat transfer through the cold-plate are discussed.

Due to the current trend of miniaturization of electronic components, higher heat fluxes are encountered. Current fan cooling methods are approaching their maximum cooling capabilities leading to the investigation of liquid cooling techniques. An experimental study of the cooling capabilities of liquid water impinging jet arrays, with a view for use in the cooling of electronic chips, is presented. The 3.0 mm thick jet nozzle plate contained 45 individual jets of 1mm diameter with 5 mm spacing between each jet. The arrays impinged onto a copper surface of 31.5 mm diameter, which dissipated approximately 200 W of heat. The inlet and outlet geometries of the jets were varied with a view of determining an optimal configuration with regards to maximum heat transfer to the impinging jets for the minimal pressure drop across the nozzle plate. Each array was tested under free-surface flow conditions, with a constant jet-to-target spacing of H/d = 20 for a Reynold’s number range of approximately 300–10,000. The results indicate that chamfering of the inlet decreased the pressure drop for a given average heat transfer coefficient, whilst chamfering of the outlet provided a greater heat transfer for a given Reynold’s number.

Making electronic products smaller in size requires air passages in the products to be narrow. For effective thermal management with natural convection, the relationship between cooling performance and a space for the air passages must be clarified. In this study, the natural cooling capacity and flow field in relatively small electronic equipment have been investigated. A channel model was used as an experimental model of electronic equipments. The channel model has two vertical copper walls modeling the printed circuit boards and two transparent walls modeling the casing walls. The walls constitute a vertical channel with the height of 120mm, the depth of 56mm, and the variable width. The width of the channel is called “a wall clearance” here and it is varied from 5mm to 15mm. The copper walls were heated using electric heaters. Temperatures in the model were measured with thermo-couples. In addition, velocity distributions in the channel were quantitatively measured using a particle image velocimetry (PIV). The natural cooling capacity was obtained as functions of the wall clearance and heating power. Temperature rise of the heated wall showed small differences with the clearances of 10 mm and 15mm. However, when the clearance was decreased to 5mm, temperature rise increased. The relationship between Nusselt number and Rayleigh number obtained in this study agrees with those obtained for the parallel plates without side walls. The results of the velocity measurement revealed that the velocity showed a 33% decrease when the wall clearance decreased from 10mm to 5mm. On the other hand, the maximum velocity in the channel showed a 10% increase when the clearance decreased from 15mm to 10mm. The changes in the velocity profiles depending on the heating conditions are clarified.

Heat transport characteristics of a closed loop pulsating heat pipe (PHP) have been investigated experimentally. The heat pipe consists of 12 turn copper pipes with 2mm inner diameter. The lengths of heating, adiabatic and cooling sections are 53mm, 100mm and 51mm, respectively. The heat load was varied up to nearly 1000W for water and R141b as the working fluid. Three kinds of orientation, bottom heat vertical, horizontal, and top heat vertical, were tested. Detailed measurements of wall temperature fluctuations for water revealed several characteristic operating behaviors, such as intermittent oscillation and thermosyphon-like behavior. The performance of PHP with R141b is better than that with water in small heat load range due to its independence of orientation, conversely, PHP with water was more efficient than R141b in large heat load range. In order to improve the performance of PHP with R141b, diamond particles were added, resulting in better performance than water in the whole range of heat load.

The results of electro-thermal analysis, which is widely known as hydrodynamic model, are strongly dependent on the mesh size of model. However, the theory and method of accurate mesh size have not been investigated. In this research, we focus on submicron Si MOSFET and show the mesh zoning method for electro-thermal analysis. First, we explain the mesh zoning method for vertical direction, i.e. the direction from the gate oxide to the bottom surface of MOSFET, which was derived from the theory of the semiconductor physics, because the calculation results were strongly dependent on the mesh size of vertical direction. Along the vertical direction, Debye length with consideration of submicron size is the most important length scale. This Debye length is not same to the conventional one. We briefly show the derivation procedure of Debye length considered submicron phenomena and the procedure of the mesh zoning method by using this Debye length. Then, we show the error of the calculation results depended on the mesh size for the lateral direction, i.e. direction from the source electrode to the drain electrode, and we investigate the most important part in MOSFET for precise calculation.