A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5°C, compared with the case in which only the wiring length is minimized.
- Heat Transfer Division
Multidisciplinary Placement Optimization of Heat Generating Semiconductor Logic Blocks
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Suwa, T, & Hadim, H. "Multidisciplinary Placement Optimization of Heat Generating Semiconductor Logic Blocks." Proceedings of the ASME 2008 Heat Transfer Summer Conference collocated with the Fluids Engineering, Energy Sustainability, and 3rd Energy Nanotechnology Conferences. Heat Transfer: Volume 2. Jacksonville, Florida, USA. August 10–14, 2008. pp. 779-787. ASME. https://doi.org/10.1115/HT2008-56056
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