A network method for quickly calculating the temperature distributions in an LSI chip with silicon-on-insulator (SOI) transistors and multi-layered lines has been developed. Its calculation time is less than 1/1000 of that of the finite element method, and its error is within 15%. The developed fast calculation method can be used in the case of more than 300 heating devices and more than 1000 lines in an LSI chip. It is thus a practical tool for designing the optimum layout of devices to prevent local temperature increases in an LSI chip.

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